The present invention relates to a lateral double diffused metal oxide semiconductor (DMOS) transistor, and more particularly, to a lateral DMOS transistor having reduced surface field (RESURF).
In general, a breakdown voltage of a lateral DMOS transistor is closely related to the thickness of an epitaxial layer. For example, when the thickness of the epitaxial layer is reduced, the breakdown voltage of the lateral DMOS transistor is reduced. Nowadays, a lateral DMOS transistor having a thin epitaxial layer and a high breakdown voltage can be fabricated by using RESURF technology.
FIG. 1 is a sectional view of a conventional lateral DMOS transistor 10. Lateral DMOS transistor 10 has an n-type drift region 12 formed on a p-type silicon substrate 11. A p-type bottom layer 13 and an n-type buried layer 14 are located along the interface between p-type silicon substrate 11 and n-type drift region 12. P-type bottom layer 13 and n-type buried layer 14 are laterally spaced a predetermined distance apart. N+-type drain region 17 and n-type buried layer 14 are formed so that n+-type drain region 17 is located above n-type buried layer 14 along the vertical dimension. A p-type top region 15 and an n+-type drain region 17 are formed in n-type drift region 12. A p-type well region 19 is formed over and in contact with p-type bottom layer 13, and a p-type body region 18 is formed over and in contact with p-type well region 19. An n+-type source region 16 is formed in p-type body region 18.
A gate insulating layer 20 is formed on portions of p-type body region 18 to which n-type drift region 12 is adjacent, n-type drift region 12, and n+-type source region 16. Then, a gate conductive layer 21 is formed on gate insulating layer 20. A source electrode 22 is formed to contact portions of n+-type source region 16 and p-type body region 18. A drain electrode 23 is formed to contact a portion of n+-type drain region 17. Gate conductive layer 21, source electrode 22, and drain electrode 23 are electrically insulated from one another by an interlevel dielectric layer 24.
A common drawback of the FIG. 1 transistor is the high electric field present at the corner of p-type top region 15 near n+-type drain region 17. N-type buried layer 14 is formed directly below n+-type drain 17 along the vertical dimension to help reduce this high electric field by absorbing some of the field. However, this structure does not result in any significant reduction in the high electric field. This high electric field at the interface between the silicon layer and oxide layer cause carriers that are generated in the depletion region to be trapped in the oxide layer, thereby deteriorating the reliability of the lateral DMOS transistor. Also, in lateral DMOS transistors, most charges of an operating current flow near the silicon surface. In the conventional lateral DMOS transistor, impact ionization is accelerated by the high electric field at the interface between the silicon layer and the oxide layer, and thus the breakdown voltage is reduced as the operating current is increased. These mechanisms are described in more detail using FIGS. 2 and 3.
FIG. 2 illustrates the electric field distribution in the lateral DMOS transistor of FIG. 1 when 600 V is applied to the drain. A region of high electric field can be seen around n-type buried layer 14. This region is shown by the cross-hatched region labeled as A. Another region of high electric field can be seen around the surface of the silicon under one end of drain electrode 23. This region is shown by the cross-hatched region labeled as A′. The carriers generated in the depletion region are accelerated by the high electric field of region A′. Consequently, the accelerated carriers are trapped in the oxide layer directly above region A′, thereby deteriorating the reliability of the device.
FIG. 3 illustrates the current density in the lateral DMOS transistor of FIG. 1 when 600 V and 6 V are applied to the drain and gate, respectively. As can be seen, most of the current bypasses p-type top region 15 and flows through the surface of the silicon layer when approaching drain electrode 23. The current is indicated by letter B. Accordingly, impact ionization is accelerated by the high electric field at the surface of the silicon layer, reducing the breakdown voltage as the current is increased.
Thus, a lateral DMOS transistor having reduced surface electric field is desirable.